A part of a typical example of a known shift register circuit is illustrated in FIGS. 1 to 3. The known shift register circuit basically comprises a plurality of stages, however FIG. 1 shows first and second stages 1 and 2, only. The first stage 1 consists of two inverter circuits 3 and 4 and two transfer gates 5 and 6 which are alternately arranged and connected in series to store a data bit D1 appearing at an input node 7 in response to a phase one (.PHI.1) clock and transfer a data bit D2 preserved therein during the previous cycle to the second stage 2 when a phase two (.PHI.2) clock goes up to a high level. The second stage 2 thus fetching the data bit D2 also consists of a combination of a transfer gate 8 and an inverter circuit 9 for storing the data bit D2 and a combination of a transfer gate 10 and an inverter circuit 11 for transferring a data bit D3 also stored therein during the previous cycle.
Each of the stages is arranged as shown in FIG. 2 and is constituted by six n-channel field effect transistors 12 to 17. The transistors 12 and 15 are clocked by the phase one (.PHI.1) clock and the phase two (.PHI.2) clock, respectively, and respectively correspond to the transfer gate 5 or 8 and the transfer gate 6 or 10 in FIG. 1. 18 and 19 indicate the respective gate capacitance of the field effect transistors 14 and 17, respectively. The shift register circuit illustrated in FIG. 1 can therefore is rewitten as illustrated in FIG. 3 in which the reference numerals used in FIG. 2 designate corresponding transistors and gate capacitances incorporated in the first stage 1 of the shift register circuit. On the other hand, reference numerals 22 to 29 designate transistors or gate capacitances of the second stage 2 corresponding to the components indicated by reference numerals 12 to 19 in FIG. 2, respectively.
Functions of the respective transistors incorporated in the conventional shift register circuit is described hereinunder on the assumption that the data bits D2 and D3 of the low level are stored in the first and second stages, respectively, and that the data bit D1 of the high level appears at the input node 7. Upon completion of the previous shift cycle, the gate capacitances 19 and 29 have been charged and caused the transistors 17 and 27 to turn on to establish current paths from output nodes 31 and 32 to the ground, respectively, then allowing the output nodes 31 and 32 to be in low levels. After the data bit of high level appears at the input node 7, the transistor 12 serving as a transfer gate turns on in response to the phase one (.PHI.1) clock to allow the data bit D1 to arrive at the gate capacitance 18, thereby preserving the data bit D1 of the high level in the form of positive charges. When the phase one (.PHI.1) clock appears, the gate capacitance 28 is still grounded through the field effect transistors 22 and 17 the former of which turns on in response to the phase one (.PHI.1) clock and the latter of which remains in on-condition by the agency of the gate capacitance 19 charged as above noted, then causing the field effect transistor 24 to remain in an off-condition. The phase one (.PHI.1) clock is simultaneously applied to the field effect transistors 13 and 23 to allow them to turn on for supplying nodes 33 and 34 with a positive high voltage level Vdd from a voltage source. When the positive voltage Vdd is supplied to the node 33, the voltage level of the node 33 is liable to go up. However, the on-resistance of the transistor 13 is selected to be sufficiently larger than that of the transistor 14, so that the node 33 remains within the low level, however a current path is established on the simultaneous on-conditions of the field effect transistors 13 and 14. On the other hand, the gate capacitance 29 do not get cancelled at this time because of the field effect transistor 24 that is in an off-condition, so that the output node 32 is still in the low level.
After accumulation of the gate capacitance 18, the phase one (.PHI.1) clock recovers from its high level to allow the field effect transistors 12, 13, 22 and 23 to turn off, and then field effect transistors 15 and 25 turn on in response to the phase two (.PHI.2) clock. When the field effect transistor 15 turns on, the positive chages accumulated in the gate capacitance 19 is allowed to propagate through the field effect transistors 15 and 14 to the ground, then causing the field effect transistor 17 to turn off. The field effect transistor 16 is also applied with the phase two (.PHI.2) clock and then turns on to supply the output node 31 with the positive high level voltage Vdd, thereby shifting the output of the first stage 1 from the low level to the high level. On the other hand, even if the field effect transistor 25 turns on in response to the phase two (.PHI.2) clock, the gate capacitance 29 is not discharged. This is because of the fact that the field effect transistor 24 remains off and, for this reason, no current path is established from the gate capacitance 29 to the ground. The gate capacitance 29 keeps the field effect transistor 27 open, so that the output node 32 remains in a low level. As a result of the shift cycle described above, the data bit D1 of the high level appears at the output node 31 and the data bit D2 of the low level is transferred from the first stage 1 to the second stage 2.
However, the conventional shift register circuit shown in FIGS. 1 to 3 has a drawback in that the current paths tend to take place between the positive voltage source Vdd and the ground, respectively. This results from the fact that the field effect transistors 13 and 14 and the field effect transistors 26 and 27 are simultaneously in an on-condition. One of the simultaneous on-conditions is described hereinbefore in connection with the transistors 13 and 14 and increases the power dissipation. Moreover, the conventional shift register circuit needs six transistors to form each stage, and, for this reason, has a complex circuit configulation.
One of the solutions proposed to reduce the power dissipation is one in which the field effect transistors 13, 16, 23 and 26 are selectively supplied with the phase one (.PHI.1) clock and the phase two (.PHI.2) clock instead of the positive voltage level Vdd. FIG. 4 shows the clock timings and the waveforms which appear at respective output nodes including the nodes 31 and 32 and an output node of the third stage (not shown). However, the complex circuit configuration still remains in the solution, and another problem is encountered in that the clock pulses (.PHI.1) and (.PHI.2) are required to drive large capacitance 18, 19, 28 and 29 and, for this reason, the clock generator (not shown) needs to have a large current driving capability, then occupying a large space.
This invention contemplates elimination of these problems inherent in the prior art or the one proposed solution.